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Design and Implementation of FPGA Controlled Buck-Boost Converter for Wide Range of Input Voltage


Author(s):

Jwala M J , Mar Athanasius College of Engineering, Kothamangalam; Anila P V, Mar Athanasius College of Engineering, Kothamangalam; Marry Joseph, Mar Athanasius College of Engineering, Kothamangalam

Keywords:

Digital control, pulse-skipping, mode-transition technique, non-inverting buck-boost converter, FPGA

Abstract:

Dead time in a synchronous controlled dc–dc converter adversely affect the stability of a four-switch non inverting buck-boost converter. The pulse-skipping phenomenon occurs in the mode-transition region near the boundary between the step-down and step-up regions, and this phenomenon leads to an unstable output voltage and an unpredictable output voltage ripple. These results may damage the entire power system and application system. This paper proposes an enhanced Duty Cycle-Overlap control technique for a digitally controlled non inverting buck-boost converter. The proposed technique offers two duty cycles limitations for various conditions in the mode-transition region and ensures the stability of the digital controller and output voltage. Moreover, this technique involves combining the duty cycles of both step-down and step-up modes for deriving an accurate value of the output voltage.


Other Details:

Manuscript Id :NCTTP012
Publication Date: 06/05/2017
Page(s): 43-47
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