Testing of Symmetric Stacking Counter

S Chandrasekaran

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25-December-22

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Testing of Symmetric Stacking Counter

Author(s):

S Chandrasekaran , AYYANADAR JANAKIAMMAL POLYTECHNIC COLLEGE,SIVAKASI,TAMILNADU

Keywords:

Multiplexer, Counter, Full adder, Fault tolerant, stacking, Read Only Memory (ROM)

Abstract:

Parallel counters are enter components in numerous number juggling circuits, particularly quick multipliers. Another paired counter plan is proposed. It utilizes Multiplexer (MUX) based full adder circuit, which aggregate the greater part of the "1" bits together. In proposed structure one xor obstruct in traditional snake is supplanted by multiplexer square with the goal that the basic way delay is limited. Counter-based systems have been proposed for use in worked in test set installing. A solitary counter or various counters might be utilized with one or different seeds. This paper concentrates on region productive blame tolerant full snake outline. This outline can repair single and twofold blame without intruding on the typical operation of a framework. A framework must be blame tolerant to diminish the disappointment rate in the blame area. In this approach self-checking full snake is utilized recognizing the blame in light of inside usefulness. The idea of self- checking and blame tolerant is acquainted with manage the issue of blame. Subsequently the operations associated with the proposed configuration is performed utilizing self-checking and mistake rectifying counter based full snake plan. Moreover, counters might be joined with Read Only Memory (ROM) proposed framework coded in Verilog Hardware Description language (VHD) and mimicked utilizing Xilinx 12.1.