Low Power High Performance Multipliers using MTCMOS Technique
Author(s):
Parul Gupta , IPEC, Ghaziabad
Keywords:
MTCMOS, Multipliers, CMOS, Low Power VLSI
Abstract:
This paper presents the power and delay optimized multipliers utilizing MTCMOS technique. Multiplier is an essential arithmetic component for any DSP application, such as filtering and fast Fourier transform (FFT). Three 8 bit multipliers i.e. Array, Braun and Baugh Wooley has been constructed on Cadence Virtuoso and results have been compared on the basis of power, delay and leakage. All the simulations have been carried out on 45nm technology.
Other Details:
Manuscript Id | : | IJSTEV5I1008
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Published in | : | Volume : 5, Issue : 1
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Publication Date | : | 01/08/2018
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Page(s) | : | 32-35
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