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Low Power High Speed Full Adder based on Pass Transistor Logic


Author(s):

Neha , Noida

Keywords:

Low Power, Full Adder, Pass Transistor, PDP, Tanner EDA

Abstract:

This paper presents a full adder using modified XNOR block to help consume less power and attain high speed. The simulation was completed utilizing standard Tanner EDA device with 180/90-nm technology. The design has been the proposed full adder offered 21.57% change regarding the past plan as far as Power Consumption (90-nm technology at 1.2 V). Relating Power change was 39.95% when a similar outline was actualized in 180-nm technology at 1.8-V power supply.


Other Details:

Manuscript Id :IJSTEV4I11043
Published in :Volume : 4, Issue : 11
Publication Date: 01/06/2018
Page(s): 77-81
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