An Improved Low Power, High Speed CMOS Adder Design for Multiplier

Author(s):

Siddharth Sharma , C-DAC Mohali ; Dr. Balwinder Singh, C-DAC Mohali; Vemu Sulochana, C-DAC Mohali

Keywords:

Transmission Gate, Low Power, Arithmetic Circuits, Low Leakage, Full Adder

Abstract:

An improved CMOS full adder circuit for high speed and low power applications is proposed in this paper at 90 nm technology node with supply voltage 1.2 V. The proposed designs contain implementation of sum and carry circuit separately. The adder circuit contains carry circuit with transmission gate logic, which is the power reduction logic in any digital circuitry. Transmission logic decrease transistor count of our proposed carry circuitry. The proposed design gives 53% reduction in power, 63 % reduction in delay, respectively. A 2-bit multiplier is made using the proposed adder circuit which results in very less power consuming and very fast in operation in compared to the other multiplier circuits.

Other Details:

Manuscript Id	:	IJSTEV4I11015
Published in	:	Volume : 4, Issue : 11
Publication Date	:	01/06/2018
Page(s)	:	29-33

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