Delay Estimation of Fast Test Pattern Generator (TPG) using Ausim L 2.3

Author(s):

G. Naveen Balaji , SNS College of Technology, Coimbatore - 35; P. Malini, SNS College of Technology, Coimbatore - 35; T. Poovika, SNS College of Technology, Coimbatore - 35; P. Shanmugavadivu, SNS College of Technology, Coimbatore - 35; I. Rinisha Prem Priya, SNS College of Technology, Coimbatore - 35

Keywords:

Linear Feedback Shift Register (LFSR), Test Pattern Generator (TPG), gate delay, propagation delay, AUSIM L2.3

Abstract:

This paper attempts to show the survey on Test pattern generator (TPG) of a 28bit LFSR with Gate delay, propagation delay, and total number of gates are listed. The circuits were built in .asl file and simulated using AUSIM L2.3. The operation of digital logic simulator called the Auburn University Simulator (AUSIM) is described. The AUSIM version L2.3 besides providing simulation of non-hierarchial circuit descriptions it also provides area and performance audits of the cell.

Other Details:

Manuscript Id	:	IJSTEV4I9052
Published in	:	Volume : 4, Issue : 9
Publication Date	:	01/04/2018
Page(s)	:	206-212

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