FPGA Implementation of New Data Transfer Data Matrix Methodology for IP Protection Scheme

Mrs. Nithya Devi; V. Gnana Merlin; S. Kavin Kumar; M. Mehala; P. Mohan Kumar

CALL FOR PAPERS : Dec-2023

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25-Dec-23

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FPGA Implementation of New Data Transfer Data Matrix Methodology for IP Protection Scheme

Author(s):

Mrs. Nithya Devi , Dr. N.G.P Institute of Technology, coimbatore; V. Gnana Merlin, Dr. N.G.P Institute of Technology, coimbatore; S. Kavin Kumar, Dr. N.G.P Institute of Technology, coimbatore; M. Mehala, Dr. N.G.P Institute of Technology, coimbatore; P. Mohan Kumar, Dr. N.G.P Institute of Technology, coimbatore

Keywords:

Field Programmable Gate Array (FPGA), Intellectual Property (IP) Protection, zero knowledge, Data matrix

Abstract:

Data matrix as a novel intellectual property (IP) protection technique can protect field programmable gate array (FGPA) IP’s from the infringement. However, the data matrix technique will protect the sensitive information during the public verification. The third party vendors cannot crack the embedded watermark to resell the design. By the zero-knowledge watermarking verification schemes, we can address the sensitive information leakage issues but are vulnerable to embedding attacks, which makes them ineffective in preventing the infringement denying of verifiers. This paper proposes a new data transfer data matrix methodology based on the chaos based zero-knowledge interaction which resists embedding attacks. The proposed method with implementation result and analysis provided a high Secured data transfer with better robustness.