Double Tail Comparator
Author(s):
Narmathashri P , velammal Engineering College; Usharani. M, Velammal Engineering College
Keywords:
Comparator, CMOS, Double Tail
Abstract:
The need for ultra-low-power, space economical and high speed analog-to-digital converters is pushing toward the utilization of dynamic regenerative comparators to maximize speed and power potency. During this project, associate analysis on the delay of the dynamic comparators are going to be given and analytical expressions are derived. From the analytical expressions, style’s will get associate intuition concerning the most contributors to the comparator delay and totally explore the trade-offs in dynamic comparator design. supported the given analysis, a brand new dynamic comparator is projected, wherever the circuit of a traditional double tail comparator is changed for low-power and quick operation even in tiny offer voltages. While not complicating the look and by adding few transistors, the feedback throughout the regeneration is reinforced, which ends up in remarkably reduced delay time. Post-layout simulation leads to a 250 µm CMOS technology ensure the analysis results. It’s shown that within the projected dynamic comparator each the facility consumption and delay time are considerably reduced. the most clock frequency of the projected comparator will be hyperbolic to a pair of.5 and 1.1 gigahertz at offer voltages of one.2 and 0.6 V, whereas overwhelming one.4mW and 153 µW, severally.
Other Details:
| Manuscript Id | : | IJSTEV4I2011
|
| Published in | : | Volume : 4, Issue : 2
|
| Publication Date | : | 01/09/2017
|
| Page(s) | : | 115-117
|
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