A Novel Low Power, High Speed Design of Phase Frequency Detector (PFD) using 180nm Technology

Author(s):

Sumit Kumar Singh , Galgotiya College of Engineering, Greater Noida; Amit Gupta, Galgotiya College of Engineering, Greater Noida

Keywords:

Phase Lock Loop, Dead Zone, Gate Diffusion Input

Abstract:

As technology is shrinking down high speed, low power device demands circuitry which works faster. Considering into account, here we proposed a new phase frequency detector (PFD) with 4 transistors. A GDI (Gate Diffusion Input) - a new technique of low power digital circuit design is used to implement new circuit. Due to less number of transistor it consume less power and gives less delay in circuit. Proposed phase frequency detector is used in phase lock loop. Proposed design gives 56% reduction in power and 76% reduction in delay. Simulation has been done in 180 nm TSMC technology CMOS environment.

Other Details:

Manuscript Id	:	IJSTEV3I8060
Published in	:	Volume : 3, Issue : 8
Publication Date	:	01/03/2017
Page(s)	:	140-143

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