Design and Implementation of High Speed Vedic Multiplier using Brent Kung Adder on FPGA

Gaurav Raj; Depanjan De

CALL FOR PAPERS : Oct-2023

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25-Oct-23

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Design and Implementation of High Speed Vedic Multiplier using Brent Kung Adder on FPGA

Author(s):

Gaurav Raj , United Institute of Technology, Allahabad, Naini; Depanjan De, United Institute of Technology, Allahabad, Naini

Keywords:

Vedic Multiplier, Xilinx, FPGA, Full Adder

Abstract:

This paper presents the design and implementation of high speed Vedic multiplier (Urdhva Tiryagbhyam algorithm) using parallel prefix adders on Virtex 6 FPGA. Brent kung adder, which is a parallel prefix adder is used for addition of partial products. Use of Brent kung adder will improve the speed of addition but hardware complexity will increase. A 16-bit and 8-bit vedic multiplier is designed using Verilog Hardware Description Language and synthesized on XiIlinx Design Suite 14.7 and simulated using Isim simulator. Compared to existing designs the proposed design is having significant improvement in delay. The proposed 16-bit/8bit vedic multiplier is having 37% and 32% improvement in delay respectively, compared to an existing recent design.