A Gate Diffused Input Based CMOS Full Adder Circuit for Low Power, High Speed Applications

Author(s):

Yamini Verma , Department of Electronics and Communication Engineering, Indira Gandhi Delhi Technical University for Women, Kashmere Gate, Delhi, India; Shivangini, Indira Gandhi Delhi Technical University for Women, Kashmere Gate, Delhi, India; Prof. Ashwani Kumar, Indira Gandhi Delhi Technical University for Women, Kashmere Gate, Delhi, India

Keywords:

adder, CMOS logic, GDI, Power gating, XNOR

Abstract:

As the technology is shrinking down we are required not only to reduce device size area but also reduce power dissipation, energy consumption and delay. Here adder circuit is the main component which is mostly used in computations that require for many applications in microprocessors. So here in this paper, our main purpose is to reduce power and delay in the CMOS adder circuit. So we have introduced a new design technique known as GDI (Gate Diffused Input) technique. GDI based full adder circuit is compared with power gating adder circuit. In power gating method, sleep transistor is used and also decreased the width, length ratio. In modified design, GDI XNOR based adder is used but it gives better results analysis than the base design. Proposed design gives the less number of transistors, low power, low energy consumption and less delay over the conventional method. Simulation has been done in the 90 nm TSMC Technology using Cadence Virtuoso tool.

Other Details:

Manuscript Id	:	IJSTEV3I12086
Published in	:	Volume : 3, Issue : 12
Publication Date	:	01/07/2017
Page(s)	:	158-163

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