Implementation of Full Adder using Single Electron Transistor, SET: The Next Generation Nano Device

Mahima U.; Priyanka N.; Manasa R.; Navya Holla K.; Chaitra A.

CALL FOR PAPERS : Apr-2023

Submission Last Date

25-Apr-23

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Implementation of Full Adder using Single Electron Transistor, SET: The Next Generation Nano Device

Author(s):

Mahima U. , DAYANANDA SAGAR COLLEGE OF ENGINEERING; Priyanka N., DAYANANDA SAGAR COLLEGE OF ENGINEERING; Manasa R., DAYANANDA SAGAR COLLEGE OF ENGINEERING; Navya Holla K., DAYANANDA SAGAR COLLEGE OF ENGINEERING; Chaitra A., DAYANANDA SAGAR COLLEGE OF ENGINEERING

Keywords:

SET, SIMON, Stability Plot, Coulomb Blockade

Abstract:

For the next generation VLSI circuits with high density, the most efficient device that can be used in basic circuits is the Single electron devices because they consume very low power and the package density. Single electron transistor [SET] is a new evolution in nanotechnology. It can be scaled to a great extent almost to that of atomic scale. It has unique characteristics of controlling one electron at a time. In an SET the number of electrons involved in logic operations is very less. Hence, the power consumption also minimizes to a great extent. As the electrons are quantized, the operating speed is very high and finds its application in many VLSI circuits. This paper presents implementation of full adder using Single Electron Transistor. It is simulated using SIMON which is IEEE standard and the results are observed. The stability analysis for the circuits designed is also done and the stability plots are obtained using SIMON. The circuits designed are found to be stable.