A Power Efficient, High Speed Reduction Technique using Domino Logic

Ms. Jyoti Chaudhary; Ms. Juhi Jain

CALL FOR PAPERS : Dec-2023

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25-Dec-23

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A Power Efficient, High Speed Reduction Technique using Domino Logic

Author(s):

Ms. Jyoti Chaudhary , Ideal Institute of Technology, Ghaziabad, AKTU, Lucknow, India; Ms. Juhi Jain, Ideal Institute of Technology, Ghaziabad, AKTU, Lucknow, India

Keywords:

Dynamic gates, evaluation phase, pre-charge phase and robustness

Abstract:

Domino logic based OR gate is proposed in this paper. Domino logic is the power reduction technique for the large circuit which uses NMOS only. In this paper we studied Previous domino logic OR gate depending on previous work. Proposed design, which is introduce new domino logic OR gate with power reduce technique and delay. We provide direct discharging path for the circuit while working. New design gives 74%reduction in power and 31% reduction in delay. Complete circuit is simulated using TSMC 90nm technology by applying 1v vdd.