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VHDL Based Design of Convolution Encoder using Vedic Mathematics and Viterbi Decoder using Parallel Processing


Author(s):

Miss. Bhagyashree V. Dagamwar , Bapurao Deshmukh College of Engg, Sevagram, Wardha; Prof. Mrs. R. N. Mandavgane , Bapurao Deshmukh College of Engg, Sevagram, Wardha; Prof. Mrs. D. M. Khatri , Bapurao Deshmukh College of Engg, Sevagram, Wardha

Keywords:

Convolutional Encoder, Multiplier, Vedic algorithm, Viterbi decoder, Parallel processing, VHDL, XILINX 14.5i

Abstract:

Convolutional encoding with Viterbi decoding is a powerful method in many communication systems due to the excellent error control performance. The Convolutional encoder encodes the message and then the encoded bits are generated. The bits which are encoded are again sent to the Viterbi Decoder and then the decoded output is obtained. This paper targets the Design of convolutional encoder using vedic mathematics and viterbi decoder using parallel processing. In mathematics, multiplication is the most commonly used operation. Hence, vedic multiplier is used in convolutional encoder. This algorithm follows a fast multiplication process and achieves a significantly less computational complexity over its conventional multipliers. In viterbi decoder, branch metric unit and add compare select unit are designed and pipeline and parallel processing concept is used to improve processing time and save memory space. Pipeline and parallel process performs more than one operation in the given period i.e. more than one input is given to the convolutional encoder and get more than one output at viterbi decoder. The simulation and synthesis of proposed design are done through XILINX 14.5i ISE Simulator tool and coding is in VHDL. It is observed that the proposed work is better in delay (processing time) than their counterparts.


Other Details:

Manuscript Id :IJSTEV3I1178
Published in :Volume : 3, Issue : 1
Publication Date: 01/08/2016
Page(s): 413-419
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