Reduction of Power Dissipation in SRAM using Adiabatic Logic

Author(s):

Sridhar S V , VTU PG Center, Belagavi; Mahesh B Neelagar, VTU PG center, Belagavi

Keywords:

5T SRAM, Adiabatic Logic, Cache Memory, SCRL, Transmission Gates

Abstract:

Static RAM is a temporary storage memory used in cache memory. It is a fast access memory and it is prone to high power dissipation. Adiabatic logic technique is one among the many low power techniques in VLSI design to reduce power dissipation. Adiabatic logic is implemented to SRAM to reduce power dissipation. Among the various adiabatic techniques, Split Level Charge Recovery Logic (SCRL) is used to reduce power dissipation in SRAM. Adiabatic logic is implemented for conventional 5T SRAM in this paper. The operation of adiabatic logic implemented SRAM is similar to the operation of conventional SRAM. Clocks have been used instead of DC supply and transmission gates are used. Size of the SRAM becomes large but it is overcome by reduction in the power dissipation. Simulation is done in 45nm technology using Cadence.

Other Details:

Manuscript Id	:	IJSTEV3I1067
Published in	:	Volume : 3, Issue : 1
Publication Date	:	01/08/2016
Page(s)	:	198-200

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