An efficient RSA algorithm using pipelined vedic multiplier

Parvathy R; Prof.G.K, Sadanandan

CALL FOR PAPERS : Mar-2023

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25-Mar-23

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An efficient RSA algorithm using pipelined vedic multiplier

Author(s):

Parvathy R , Toc H Institute of Science and Technology, Arakkunnam; Prof.G.K, Sadanandan, Toc H Institute of Science and Technology

Keywords:

Cipher text, Modular exponentiation, RSA algorithm, Urdhva tiryagbhyam sutra, Vedic multiplier

Abstract:

Multipliers are the essential and abundant part of DSP applications. There are different types of multipliers are used to perform various applications. Array multipliers, Vedic multipliers are two different types of multipliers. Based on the comparative study, it is proved that Vedic multipliers are much faster than array multipliers. The speed of operation is further improved by introducing a pipelined architecture to the conventional Vedic multipliers so that it can be used in very complex multiplication based systems. RSA algorithm is one such popular algorithm which is used for security of networks. It includes several time consuming exponentiation operations based on multiplications. Therefore the proposed pipelined Vedic multiplier based on Urdhva Tiryagbhyam Sutra is applied to RSA to enhance the speed of operation. The design is done using ModelSim and implemented using Xilinx.