High Efficient Carry Select Adder
Author(s):
Shiya Andrews V , Saintgits College of Engineering, Pathamuttam, Kerala; Jyothis Candran G, Saintgits College of Engineering
Keywords:
Adder, Arithmetic Unit, Low Power Design
Abstract:
Design of high speed, area efficient and low power logic systems is the main challenge of VLSI system design. Adder circuit is the main building block of the digital system. But digital adders suffer with the problem of carry propagation delay. To deaden this problem, Carry Select Adder (CSLA) is used in computational circuit. In this paper, the logic operations involved in conventional CSLA, modified Binary To Excess-1 Converter (BEC) based CSLA and Common Boolean Logic (CBL) based CSLA are analysed to study the data dependencies and thereby identify and decimate the redundant logic operations. In the modified scheme, the carry select (CS) operation is done before the calculation of the final sum. The modified CSLA involves less area and delay than the CBL based CSLA.
Other Details:
| Manuscript Id | : | IJSTEV2I4101
|
| Published in | : | Volume : 2, Issue : 4
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| Publication Date | : | 01/11/2015
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| Page(s) | : | 284-294
|
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