Power Efficient Dual Dynamic Node Flip Flop with Embedded Logic by Adopting Pulse Control Scheme

Author(s):

Thara Sebastian , Saintgits College of Engineering, pathamuttom; Aravindhan A, Saintgits college of Engineering

Keywords:

Conditional Pulse Enhancement, Dual Dynamic Node, Embedded Logic, Flip Flop (FF), Pass Transistor AND, Pulse Generation

Abstract:

In this paper a low power conditionally pulse enhanced dual dynamic node flip flop design is presented. The proposed structure combines the merits of dual dynamic node and a pulse control scheme (PCS) named conditional pulse enhancement mechanism. It eliminates the large capacitance present in the precharge node of several conventional designs by following a split dynamic node structure to separately drive the output pull-up and pull-down transistors. The conditional pulse enhancement scheme consists of a simple pass transistor ‘AND’ gate design and a pull up ‘pMOS’. This set up reduces circuit complexity and removes the pulse generation control logic from the critical path, which facilitate a faster discharge operation as well as improvise the discharge speed conditionally. Various pre-layout simulation results based TSMC 180-nm technology reveal that the proposed design features the best power-delay-product performance compared to SDFF, HLFF, and DDFF. It also presents an area, power, and speed efficient method to incorporate complex logic functions into the flip flop. The performance improvements indicate that the proposed designs are well suited for modern high-performance designs where power dissipation and latching overhead are of major concern

Other Details:

Manuscript Id	:	IJSTEV2I4083
Published in	:	Volume : 2, Issue : 4
Publication Date	:	01/11/2015
Page(s)	:	256-264

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