Parallel Self Timed Adder Using Gate Diffusion Input Logic

Elina K Shaji; Abraham K Thomas; Susan Abe

CALL FOR PAPERS : Mar-2023

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25-Mar-23

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Parallel Self Timed Adder Using Gate Diffusion Input Logic

Author(s):

Elina K Shaji , SAINTGITS COLLEGE OF ENGINEERING; Abraham K Thomas, SAINTGITS COLLEGE OF ENGINEERING; Susan Abe, SAINTGITS COLLEGE OF ENGINEERING

Keywords:

Asynchronous Circuits, Binary Adders, CMOS Design

Abstract:

In modern technology, power dissipation has become a major and vital constraint in electronic industry. Gate diffusion Input (GDI) is a technique that lowers power dissipation to a greater extend. This technique also reduces the transistor count, area and thus the complexity of the circuit. The circuit will be much simpler and easy to manage. This paper describes the design of a 16 bit Parallel Self Timed Adder (PASTA) using GDI logic. PASTA is an asynchronous adder and is based on a recursive formulation for performing multi-bit binary addition. The operation of PASTA is parallel for those bits that do not require any carry chain propagation. PASTA design uses multiplexers along with half adders. All the carriers are detected using a completion signal detection unit which will enable the selection line of multiplexer which produces high fan out. One of the limitations is high fan in, but this is unavoidable for asynchronous logic. The simulation results show the proposed model attains better power consumption and reduction in number of transistors.