VLSI Architecture for 2-D Sub-band Wavelet Transform using 9/7 Wavelet Coefficient

Author(s):

AKANKSHA YADAV , HINDUSTAN COLLEGE OF SCIENCE & TECHNOLOGY ,FARAH , MATHURA(INDIA); ANUSHREE, HINDUSTAN COLLEGE OF SCIENCE & TECHNOLOGY ,FARAH , MATHURA(INDIA)

Keywords:

Resister Transistor Logic (RTL), 9/7 Filter Coefficient, Sub-band Wavelet Transform ,NEDA, Xilinx Simulation

Abstract:

Two dimensional (2-D) discrete wavelet transform (DWT) is widely used in image and video compression. DWT is computational intensive so it demands real time processing. Several architectures have been suggested for efficient VLSI implementation of 2-D DWT for real-time applications. We found that multipliers consume more chip are and increases complexity of the DWT architecture. Multiplier-less hardware implementation approach provides a kind of solution to this problem due to its scope for lower hardware-complexity and higher throughput of computation. Several designs have been proposed for the multiplier-less implementation of DWT based on the principle of distributed arithmetic (DA). We found that DA requires ROM and size of ROM increases exponentially as the increase in no. of inputs, which highly increases the complexity. We have proposed a multiplier-less 2-D DWT architecture using new efficient distributed arithmetic algorithm (NEDA). NEDA is efficient algorithm, which does not require ROM. NEDA consist of adders as main component and free from multiplications and subtraction. We have proposed two architectures using NEDA and using modified NEDA. The proposed architecture using NEDA provides less delay and minimum number of slice compared the existing architecture. The proposed architecture is suitable for high speed on-line applications. It has 100% hardware utilization efficiency.

Other Details:

Manuscript Id	:	IJSTEV2I3009
Published in	:	Volume : 2, Issue : 3
Publication Date	:	01/10/2015
Page(s)	:	43-48

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