FPGA Implementation of FFT using Heterogeneous Adder

Shweta S Halakarni; Mahesh Neelagar

CALL FOR PAPERS : Mar-2023

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25-Mar-23

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FPGA Implementation of FFT using Heterogeneous Adder

Author(s):

Shweta S Halakarni , Center for PG Studies, Visvesvaraya Technological University, Belagavi, Karnataka, India; Mahesh Neelagar, Center for PG Studies, Visvesvaraya Technological University, Belagavi, Karnataka, India

Keywords:

Fourier Transform (FFT), Ripple Carry Adder, Carry look ahead Adder, Carry Select Adder, Heterogeneous Adder, VHDL

Abstract:

In digital signal processing Fast Fourier Transform (FFT) algorithm is one of the most widely used block. The adders which plays an important role in Fast Fourier Transform (FFT). To obtain optimized Adder design in terms of delay and area many researchers have been carried out. Here, we proposed adder called heterogeneous adder which is the combination of different sub adders like ripple carry adder, carry look ahead adder, carry select adder which not only reduces delay and area but also increases the speed. These heterogeneous adders are used to design Fast Fourier Transform (FFT) architecture instead of conventional adders. In this, we have proved that Fast Fourier Transform (FFT) with heterogeneous adder gives better performance in terms of delay, area with increase in speed compared to Fast Fourier Transform (FFT) with homogeneous adder that is conventional adder. The Fast Fourier Transform (FFT) with heterogeneous adder is coded in VHDL language. Simulation is done on XILINX 14.5i tool, implemented on SPARTAN-6 kit. Overall delay and area are reduced with increase in speed.