FPGA Implementation of Low Area Single Precision Floating Point Multiplier

Author(s):

Mamatha M , KALPATARU INSTITUTE OF TECHNOLOGY,TIPTUR; S Pramod Kumar, assistant professor, kalpataru institute of technology, tiptur

Keywords:

floating point; multiplication; FPGA; vedic multiplier (VM)

Abstract:

In this paper depict an effective usage of an IEEE 754 single precision floating point multiplier focused for Xilinx Spartan 3E FPGA. Verilog HDL is utilized to actualize an innovation. The multiplier execution handles the overflow and underflow cases. Adjusting is not actualized to give more accuracy when utilizing the multiplier as a part of a multiply and Accumulate (MAC) unit. The multiplier was confirmed against Xilinx floating point multiplier center produced by Xilinx coregen. By using 24*24 Nikhilam vedic sutra for multiplication reduces the area of proposed design, It reduces the large multiplying numbers into smaller values.

Other Details:

Manuscript Id	:	IJSTEV2I11135
Published in	:	Volume : 2, Issue : 11
Publication Date	:	01/06/2016
Page(s)	:	560-566

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