Optimum Analysis of ALU Processor by Using UT Techniqu

Author(s):

RAHUL SHARMA , Vidhyapeeth Institute of Science and Technology Bhopal, MP, India; DEEPAK KUMAR, Vidhyapeeth Institute of Science and Technology Bhopal, MP, India

Keywords:

Vedic mathematics, Adder, Multiplication, Urdhva Tiryakbhyam (UT) Technique, Multiplexer

Abstract:

Now a day's, the main challenge in front of VLSI System designer are to design fast processing system. And the ALU are main functional unit in most digital and high performance systems such as FIR filters, digital signal processors and microprocessors etc. So the performance such VLSI circuit is dependent on the performance of the ALU. And the ALU speed is mainly depends on the speed of multiplier. Here, a High-speed multiplier is designed and analyzed which is based on the algorithm named as “Urdhva Tiryakbhyam” sutra (UT Technique). Traditionally, this well known Technique has been used for fast multiplication. And analyze in terms of Path delay and there by efficiency. The proposed algorithm is developed using VHDL. Implementation has been done using Xilinx14.2, Spartan 6.

Other Details:

Manuscript Id	:	IJSTEV2I10115
Published in	:	Volume : 2, Issue : 10
Publication Date	:	01/05/2016
Page(s)	:	499-503

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