PERFORMANCE IMPROVEMENT OF LOW POWER SCALABLE TURBO DECODER USING NoC ARCHITECTURE
Author(s):
M.Loga lakshmi , CCET, Oddanchatram, Tamilnadu – 624619; M. Nithya, CCET, Oddanchatram, Tamilnadu – 624619; J. Nivetha, CCET, Oddanchatram, Tamilnadu – 624619; R. Shruthi Eshwari, CCET, Oddanchatram, Tamilnadu – 624619
Keywords:
Turbo Decoders, Noc, VLSI, Finite State Machine Approach
Abstract:
this work proposes a general framework for the design and simulation of network on chip based turbo decoder architectures. Network on chip or network on a chip (NoC or NOC)is a communication subsystem on an integrated circuit typically between IP cores in a system on a chip(SOC).this explains a network on chip(NoC)structure for turbo decoders. Based on this analysis finite state machine approach are proposed for reducing the complexity of the NoC. Effective architecture level changes of MASIP is used for performance improvement. Here we are analysing the performance of area, power, speed and comparing the results of existing one.
Other Details:
| Manuscript Id | : | IJSTEV2I10061
|
| Published in | : | Volume : 2, Issue : 10
|
| Publication Date | : | 01/05/2016
|
| Page(s) | : | 249-254
|
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