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Real Time Trace Based Silicon Debug Infrastructure for SoCs with Distributed Trace Buffer


Author(s):

Bini V K , FISAT

Keywords:

Design For Debug, Embedded logic analysis, Intellectual Property, post silicon validation, real time observability

Abstract:

Multi-core processors brings a much higher level of flexibility to the designer. Due to the increased design complexity, the existing verification techniques are insufficient for eliminating design errors before the design is manufactured. Tracing internal signals during circuit’s normal operation, provides real-time visibility to the circuit under debug. The decisions on when to acquire debug data during post-silicon validation are determined by trigger events that are programmed into on-chip trigger units. Trace buffer such as embedded memories are used to capture debug data during in-system silicon debug. At the end of the debug session, the trace buffers can be offloaded through a trace port such as the JTAG interface for post-processing.


Other Details:

Manuscript Id :IJSTEV4I6022
Published in :Volume : 4, Issue : 6
Publication Date: 01/01/2018
Page(s): 89-95
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