Design and Implementation of AMBA APB Bridge with Low Power Consumption

Sandeep Jagre; Dr. Neelesh Gupta; Nishi Pandey

CALL FOR PAPERS : Sep-2023

Submission Last Date

25-Sep-23

Submit Manuscript Online

FOR AUTHORS

FOR REVIEWERS

ARCHIEVES

DOWNLOADS

Open Access

Design and Implementation of AMBA APB Bridge with Low Power Consumption

Author(s):

Sandeep Jagre , TRUBA COLLEGE OF SCIENCE AND TECHNOLOGY; Dr. Neelesh Gupta, TRUBA COLLEGE OF SCIENCE AND TECHNOLOGY; Nishi Pandey, TRUBA COLLEGE OF SCIENCE AND TECHNOLOGY

Keywords:

AMBA, AHB, APB, Soc (System on Chip), Clock Skew, FSM

Abstract:

The aim of the dissertation is to put in force AMBA-APB (Advance Microcontroller Bus Architecture-Advance Peripheral Bus) Bridge with efficient deployment of gadget assets. For this, simulation and synthesis of the complex bridge interface is designed which could offer minimum electrical power strength consumption and high frequency band width among AMBA high performance or speedy or high velocity buses like ASB and low active APB buses. For designing any type of IC three main criteria’s are speed, power and area. Clock is a first-rate situation in designing of any digital sequential gadget. Clock skew is generated when the distinction in clock signal arriving time between two adjacent register. One of the strategies to limit clock skew is master slave flip-flop. So in this dissertation work we used flip-flop as a memory element with master slave concept which is based on the finite state machine. Advanced Peripheral Bridge with clock skew reduction technique is enforced within the thesis the usage of Verilog HDL. For the simulation and synthesis motive, design usage summary and power details Xilinx’s-ISE design suite, model 14.1 has been used. Power record is added for developing better know-how of the energy utilization in any gadget. The power document offers the electricity consumption precise. Hence, the whole clocks energy intake is of 0.35 mW, general hierarchy strength consumption of 0.13 mW and general on chip logical strength consumption of 0.040 W had been extracted from Xilinx X-Power analyser device when APB Bridge is designed beneath the proposed design technique.