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Physical Design Implementation of Area Optimized, High Performance SRAM Cell


Author(s):

Ankita Ashok Taiwade , Dr. Babasaheb Ambedkar College Of Engineering And Research, Nagpur; Aishwarya Ashok Gode, DBACER; Shreya Shriram Bujade, DBACER; Shipra Wamanrao Sambhare, DBACER; Preeti M. Dixit, DBACER

Keywords:

SRAM Cell, Read/Write Operation, Microwind EDA

Abstract:

In the recent years, on chip memory complexities has been increased with the increase in the logic of the processor designed. So the basic element of the memory design is SRAM cell. This paper presents the idea of an 8T CMOS SRAM cell. It also implements the development and design of CMOS based SRAM cell which improves the performance, reduces the power & area requirement. This cell design is basically proposed for the power reduction during write operation. The performance of the proposed cell structure is compared with conventional 6T design in 32nm, 45nm, 65nm CMOS technologies by using Micro wind 3.5 EDA tool.


Other Details:

Manuscript Id :IJSTEV3I9156
Published in :Volume : 3, Issue : 9
Publication Date: 01/04/2017
Page(s): 545-548
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