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Efficient Hardware Implementation of Coding Schemes for Fault Tolerant Parallel Filters


Author(s):

Harsimranjeet Singh , Chandigarh Engineering College, Mohali, Punjab, India; Paramveer Singh Gill, Chandigarh Engineering College, Mohali, Punjab, India

Keywords:

FPGA Implementation, Fault Tolerant Codes, Digital Filters, Error Correcting Codes

Abstract:

This paper presents a novel scheme for the implementation of fault tolerant parallel filters. The proposed scheme exploits the linearity of filters to implement an error correction mechanism. In particular, two redundant filters whose inputs are linear combinations of the original filter inputs are used to detect and locate the errors. The coding of those linear combinations was formulated as a general problem to then show how it can efficiently be implemented. The practical implementation was illustrated with two case studies that were evaluated for an FPGA implementation and compared with a previously proposed technique.


Other Details:

Manuscript Id :IJSTEV3I9148
Published in :Volume : 3, Issue : 9
Publication Date: 01/04/2017
Page(s): 420-423
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