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A Double-Tail Comparator with Reduced Delay and Low Power Dissipation


Author(s):

Anika Kuchhal , Galgotiya College of Engineering, Greater Noida; Prakash Chandra Joshi, Galgotiya College of Engineering, Greater Noida

Keywords:

Double-Tail Comparator, Dynamic Clocked Comparator, High-Speed Analog-To-Digital Converters (ADCS), Low-Power Analog Design

Abstract:

An increase in demands of technology which consumes low power and provides minimum delay while working. Considering this in our mind we proposed a new double-tail comparator which provides digital signal when analog signal is applied as input. A proposed comparator is made up of power gating technique, which reduces power consumption in circuit by shutting down of unnecessary current in blocks when there is no need of that part in working. Test structures of the comparators, designed in TSMC180 nm are measured to determine offset –voltage, power - dissipation and speed. These are compared and the superior features of the proposed comparator are established.


Other Details:

Manuscript Id :IJSTEV3I8062
Published in :Volume : 3, Issue : 8
Publication Date: 01/03/2017
Page(s): 144-149
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