Design of Low Swing and Multi Threshold Voltage based Low Power 12T SRAM Cell: A Review

Author(s):

Diwakar Prasad Tiwari , IES College of Technology, Bhopal; Ashish Raghuwanshi, IES College of Technology, Bhopal

Keywords:

Charge Sharing, Leakage Low Power, Static Noise Margin, SRAM Swing Voltage

Abstract:

This paper focuses on the design of a novel low power twelve transistor static random access memory (12T SRAM) cell. In the proposed structure two voltage sources are used, one connected with the bit line and the other one connected with the bit-bar line in order to reduce the swing voltage at the output nodes of the bit and the bit-bar lines, respectively. Reduction in swing voltage reduces the dynamic power dissipation when the SRAM cell is in working mode. Low threshold voltage (LVT) transmission gate (TG) and two high threshold voltage (HVT) sleep transistors are used for applying the charge recycling technique. Stability of the proposed SRAM has also improved due to the reduction in swing voltage. Simulation results of power dissipation, access time, current leakage, stability and power delay product of the proposed SRAM cell have been determined and compared with those of some other existing models of SRAM cell. Simulation has been done in 45 nm CMOS environment. Tanner Tool is used for schematic design and layout design purpose.

Other Details:

Manuscript Id	:	IJSTEV3I7046
Published in	:	Volume : 3, Issue : 7
Publication Date	:	01/02/2017
Page(s)	:	163-165

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