Optimization of Power and Delay In Nonlinear Interconnects by using Schmitt Trigger

Author(s):

M. Jayanthi , PSNA COLLEGE OF ENGINEERING AND TECHNOLOGY,DINDIGUL; S. Hemalatha, PSNA College of Engineering and Technology, Dindigul-624619

Keywords:

Schmitt Trigger, Buffer, Interconnect, VLSI, DSM

Abstract:

Interconnect delay and power is a primary criterion in design of an Integrated Circuit due to its close relationship to the speed of IC. Interconnect Buffers in very large scale integration (VLSI) circuits is most common method used to reduce power and delay but they result in high Delay and power dissipation, thereby degrading the performance (i.e.) operating speed of an integrated circuit. Use of buffers in interconnect is mainly for optimizing power dissipation and delay in interconnect, but Buffers themselves have certain switching time that contributes to crosstalk delay and power dissipation. For efficiently minimizing both delay and power dissipation in long interconnects is done by replacing buffers with Schmitt Trigger in the Nonlinear Interconnect. since Schmitt trigger have low threshold voltage, Schmitt trigger allows the reduction in rise time and hence saves in terms of total delay. The proposed Schmitt trigger have larger band gap so it reduces the noise compare to that buffer.

Other Details:

Manuscript Id	:	IJSTEV3I6057
Published in	:	Volume : 3, Issue : 6
Publication Date	:	01/01/2017
Page(s)	:	86-90

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