An Efficient D-Flip Flop Using Current Mode Signalling Scheme

Author(s):

SHEONA VARGHESE , SAINTGITS COLLEGE OF ENGINEERING,KOTTAYAM,KERALA; ANU RAJ, SAINTGITS COLLEGE OF ENGINEERING; JYOTHISH CHANDRAN G, SAINTGITS COLLEGE OF ENGINEERING

Keywords:

Conditional Pulse Enhancement Scheme, Dual Dynamic Node, Current Mode Pulsed, Current Mode Clocked, Clock Gating, Transmission Gate

Abstract:

In this paper a power efficient D-flip flop was conducted by adopting a current mode signalling scheme (CMS), named current mode clocked D-flip flop. For providing full swing output proposed D-flip flop is constructed by transmission gate with Clock gating. This setup reduces the dynamic power dissipation and also reduces the circuit complexity. In this project, the effect of current mode scheme on power as well as performance of flip flop such as MS D-FF, DDFF, CPEFF and CMPFFE are analysed. The performance analysis was carried out by adopting 180nm CMOS technology. Experimental results reveal that current mode clocked D-flip flop outperforms the conventional flip flop in terms of power, delay and power delay product.

Other Details:

Manuscript Id	:	IJSTEV3I2109
Published in	:	Volume : 3, Issue : 2
Publication Date	:	01/09/2016
Page(s)	:	280-285

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