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Design Approach for Fault Recoverable high speed ALU with Improved Fault Tolerance


Chethana.D.M. , Department of VLSI Design and Embedded Systems Center for PG Studies, Visvesvaraya Technological University, Belagavi, Karnataka, India; T.C.Thanuja, Department of VLSI Design and Embedded Systems Center for PG Studies, Visvesvaraya Technological University, Belagavi, Karnataka, India


Critical ALU, Fault tolerance, Fault recovery, FSM Technique


Fault tolerance and fault recoverable ALU System with a new design approach has been proposed in this paper. Reliability is an important aspect in designing any integrated circuit. The product approval in critical applications like medical and military applications depends entirely on the reliability factor. Introduction of separate modules to the existing design for the purpose of increasing the reliability leads to the increase in area and power. An efficient approach to this problem is to utilize the already existing components in the digital system in a reasonable way to implement the recoverable techniques. Triple modular redundancy (TMR) [1] is the long back traditional approach utilized in protecting the digital system from Single event Upset (SEUs).This TMR technique is triplication of the critical components of the systems to get the fault tolerance system. The three ALUs are utilized in the design for the purpose of reliability maintenance so that if failure of one or more critical components leads to the takeover by the other. In our design if two ALUs or three ALUs failure occurs, then the critical ALU will take over the system by maintaining the reliability factor. The critical ALU is functional only in the worst case condition of failure of two or three ALUs. The Reliability of Critical ALU is verified by introducing the fault and the tolerance level of critical ALU is increased by using FSM Technique.

Other Details:

Manuscript Id :IJSTEV3I1155
Published in :Volume : 3, Issue : 1
Publication Date: 01/08/2016
Page(s): 336-341
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