IJSTE

CALL FOR PAPERS : Sep 2017

Submission Last Date
25-Sep--17
Submit Manuscript Online

FOR AUTHORS

FOR REVIEWERS

ARCHIEVES

DOWNLOADS

Open Access



CopyScape
Creative Commons License

FPGA Implementation of High Speed Floating Point Mutliplier using Log Based Design


Author(s):

Kanika Bhardwaj , Ideal College of Engineering & Technology, Ghaziabad; Juhi Jain, Ideal College of Engineering & Technology, Ghaziabad; Rakhi, Ideal College of Engineering & Technology, Ghaziabad

Keywords:

FPU, Floating Point Multiplier, FPGA Implementation

Abstract:

Floating point multiplication is a crucial operation in high power computing applications such as image processing, signal processing etc. Multiplication of floating point numbers found extensive use in DSP applications involving huge range. And also multiplication is the most time and power consuming operation. This paper proposes an efficient method for IEEE 754 floating point multiplication which gives a better implementation in terms of delay. The proposed log based Floating point Multiplier is designed using Verilog HDL and targeted on Spartan 6 FPGA.


Other Details:

Manuscript Id :IJSTEV3I11091
Published in :Volume : 3, Issue : 11
Publication Date: 01/06/2017
Page(s): 366-369
Download Article

IMPACT FACTOR

3.905

NEWS & UPDATES

Submit Article

Dear Authors, You can submit your article to our journal at the following link: http://www.ijste.org/Submit

Impact Factor

The Impact Factor of our Journal is 4.753 (Year - 2016)
3.905 (Year - 2015) 2.895(Year -2014)

Click Here

Submit Payment Online

Dear Authors, Now you can submit the payment receipt to our journal online at the following link: index.php?p=Payment

IC Value

ThVe IC Value of our journal is 62.78
Click Here

GLOBAL INDEXING



















Computer Science Directory. We are listed under Computer Research Institutes category

Share on Social media

Home | Privacy Policy | Terms & Conditions | Refund Policy | Feedback | Contact Us
Copyright © 2014 ijste.org All rights reserved