A Novel Design of 12T SRAM Cell using MT CMOS Technique on 45 nm Technology
Aditya Vikram , Galgotia College of Engg and Tech. Greater noida, Uttar Pradesh-201306; Amit Gupta, Galgotia College of Engg and Tech. Greater noida, Uttar Pradesh-201306
Transmission Gate, Leakage Low Power, SRAM Swing Voltage, Tanner Tool
As technology is shrinking down high speed, low power device demands memory which works faster. Considering into account, here we proposed a new 12 T SRAM cell which works faster and consume less power compared to present other memory cell. A new design contain transmission gate as an access transistor .Simulation results of power dissipation, access time, current leakage, stability and power delay product of the proposed SRAM cell have been determined and compared with those of some other existing models of SRAM cell. Proposed design gives 60% reduction in power. Simulation has been done in 45 nm CMOS environment. Tanner Tool is used for schematic design and layout design purpose.
|Manuscript Id ||:||IJSTEV3I10099|
|Published in ||:||Volume : 3, Issue : 10|
|Publication Date||:|| 01/05/2017|