Adiabatic Logic Circuits for Low Power, High Speed Applications
Satyendra Kumar , Shambhunath Institute of Engineering and Technology, Jhalwa, Allahabad, Uttar Pradesh; Ram Raksha Tripathi, Shambhunath Institute of Engineering and Technology, Jhalwa, Allahabad, Uttar Pradesh
PFAL, VLSI, CMOS Logic, Adiabatic Logic, MUX, Adder
As technology is shrinking down we requires devices which consume less power gives less delay in device. So here we compare PFAL (Positive Feedback Adiabatic Logic) and ECRl (Efficient Charge – Recovery Logic) technique basic logic gates with CMOS gates. Results gives improvement in power and delay. Using this ECRL and PFAL we have design 2:1 mux which is very less power consuming and fast in operation. Simulation result is done using TSMC180nm technology on tanner tool.
|Manuscript Id ||:||IJSTEV3I10063|
|Published in ||:||Volume : 3, Issue : 10|
|Publication Date||:|| 01/05/2017|