Implementation of Error Correction Technique Using OCC on FPGA

Sameer Nandanwar; Neha Tawade; Sanjana Deshmukh; Deepika Borkar; Prof. V. P. Meshram

CALL FOR PAPERS : Dec-2023

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25-Dec-23

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Implementation of Error Correction Technique Using OCC on FPGA

Author(s):

Sameer Nandanwar , Rashtrasant Tukdoji Maharaj Nagpur University; Neha Tawade, Rashtrasant Tukdoji Maharaj Nagpur University; Sanjana Deshmukh, Rashtrasant Tukdoji Maharaj Nagpur University; Deepika Borkar, Rashtrasant Tukdoji Maharaj Nagpur University; Prof. V. P. Meshram

Keywords:

Orthogonal code, Antipodal code, Error correction and detection, FPGA

Abstract:

When data is transmitted through a channel (wired or wireless), some noises may affect the reliability of data. Because of this actual information get changed. This referred as error. Therefore error detection and correction techniques are required at the receiver. Orthogonal code is one of the coding techniques which detect as well as correct the corrupted data. In this method each k-bit data set is converted into n-bit orthogonal code. An n-bit orthogonal code contains n/2 1’s and n/2 0’s, that means parity of this code is always zero. In this paper we present a new methodology to enhance the error correction capability of orthogonal code. This technique is implemented using VHDL and field programmable gate array (FPGA).