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Modified Ultra-Low Power NAND Based Multiplexer and Flip-Flop


Author(s):

Amit Saraswat , Chandigarh Engineering College, Mohali, Punjab, India; Chanpreet Kaur, Chandigarh Engineering College, Mohali, Punjab, India

Keywords:

NAND LATCH, FLIP FLOP, PDP, Low Power VLSI, CMOS Technology

Abstract:

In this paper an ultra-low power NAND based multiplexer and flip flop is proposed. The modified design is compared to conventional 4*1 multiplexer and shows dynamic and static power reduction up to 32.077% and 45.055% respectively while for JK flip flop, dynamic and static power reduction up to 84.25% and 92.47%respectively. Simulations have been done on 270C temperature and 50MHz frequency. With every selection line input dynamic power consumption is calculated, static power consumption, delay and power delay product. The simulations have been carried out on Tanner EDA.


Other Details:

Manuscript Id :IJSTEV2I6057
Published in :Volume : 2, Issue : 6
Publication Date: 01/01/2016
Page(s): 99-103
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