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Fault Tolerant NoC with Priority Based Arbiter


Author(s):

Priyanka V S , SAINTGITS COLLEGE OF ENGINEERING; Binu K Mathew, SAINTGITS COLLEGE OF ENGINEERING

Keywords:

Adaptive Algorithm, Dynamic Reconfiguration, Network-On-Chip (Noc), Reliability, System-On-Chip (Soc).

Abstract:

The proposed NoC is a fault tolerant network-on-chip with a priority based arbiter. It is based on new error detection mechanisms suitable for dynamic NoCs and here the number and position of processor elements or faulty blocks vary during runtime. Also it provides online detection of data packet and adaptive routing algorithm errors. These mechanisms are able to distinguish permanent and transient errors and also it can localize accurately the position of the faulty blocks in the NoC routers. Also an arbiter is used here for managing multiple data’s simultaneously.


Other Details:

Manuscript Id :IJSTEV2I4082
Published in :Volume : 2, Issue : 4
Publication Date: 01/11/2015
Page(s): 205-213
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