High Speed LUT-SR Family of Random Number Generation

Author(s):

Remya Justin , SAINTGITS COLLEGE OF ENGINEERING, PATHAMUTTAM, KOTTAYAM; Binu K Mathew, Saintgits College of Engineering; Susan Abe, Saintgits College of Engineering

Keywords:

Field Programmable Gate Array (FPGA), Look Up Table (LUT), Random Number Generator (RNG), Shift Register (SR)

Abstract:

FPGA Optimized RNGs are more resource efficient than software based RNGs. One type of FPGA RNG called LUT-SR RNG in which LUTs are configured into shift registers with varying length. LUT-SR generators are used to achieve high quality, long period RNG with minimum resources. Time delay is a factor which determines the bit rate. The aim of this work is to reduce the time delay of the LUT-SR RNG to provide high speed of operation. The paper describes long period LUT-SR RNG with high bit rate by combining identical blocks of short period LUT-SR RNGs. The proposed generator gives same maximum length random sequence with lesser time delay when compared with the existing LUT-SR RNG. This modified generator provides good quality generator than the existing generator.

Other Details:

Manuscript Id	:	IJSTEV2I4064
Published in	:	Volume : 2, Issue : 4
Publication Date	:	01/11/2015
Page(s)	:	182-187

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