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FPGA implementation and Design of low power sequential filter


Author(s):

Shivam Singh Sikarwar , Lord Krishna College Of Technology Indore (M.P), India; Deepak Sharma, Lord Krishna College Of Technology Indore (M.P), India73899

Keywords:

FIR Filter, Implementation of FIR Filter, Micro Programmed Controller

Abstract:

We will present the design and FPGA implementation of sequential digital 8-tap FIR filter using a novel micro programmed controller based design approach. In this paper, the FIR filter is designed for operation controls by micro programmed controller. The proposed FIR filter will be coded in VHDL using modular design approach, and implement in Spartan-3E FPGA. The performance evaluation and synthesis results obtained through Xilinx ISE synthesis tool and functionally checked in Model sim module.


Other Details:

Manuscript Id :IJSTEV2I3012
Published in :Volume : 2, Issue : 3
Publication Date: 01/10/2015
Page(s): 54-58
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