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Design and Analysis of Double Tail Comparator using Adiabatic Logic


Author(s):

Vaishnvi jumade , G.H.R.A.E.T, Nagpur; Asstt. Prof. Amol Boke, G. H. R. A. E.T

Keywords:

Conventional comparator, Dynamic Double tail comparator, adiabatic logic circuit, high-speed Analog-to-Digital Converters (ADC’s), tanner EDA

Abstract:

Nowadays the comparators are most widely used in high speed applications such as analog–to-digital converters which require high speed and low power. Hence the demand of high speed comparators with less delay and power is increasing. This paper presents the use of the double tail comparator for the faster operation with low power even at small supply voltage. A new modified double tail comparator circuit is designed by applying adiabatic logic circuit and also by adding few switching transistors to dynamic double tail comparator circuit. It is shown that in the modified circuit both the power and delay is reduced significantly even in small supply voltage. The design of proposed comparator has preamplifier stage and latching stage which increases the speed of the device. The design is simulated in 0.18um CMOS technology using tanner EDA tools which confirm the analysis results. The major objective of this paper is to reduce the power of modified double tail comparator for high speed application.


Other Details:

Manuscript Id :IJSTEV2I12222
Published in :Volume : 2, Issue : 12
Publication Date: 01/07/2016
Page(s): 586-592
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