A Power Analysis of SRAM Cell using 12t Topology for Faster Data Transmission

Author(s):

Priya Vilas Thakare , G.H.Raisoni Academy college of engineering and Technology, Nagpur; Sanjay Tembhurne, G.H.R.A.E.T, Nagpur

Keywords:

SRAM Cell, CMOS, leakage current, power, 12T SRAM Cell, read, write

Abstract:

High Power Consumption Rate of the Chips is one on the major problems faced by the circuit designers in today’s world. This paper represents an improved 12T Static Random Access Memory (SRAM) cell with the following advantages – reduced leakage current and enhanced performance, by using 180NM Technology. The SRAM cell is the need of high speed digital computing system. The switching of the transistors and leakage current during the off state of device results in more power consumption in the digital cell. To compare the proposed work with existing structure available with 12T, the proposed design gives the following advantages: reduction in the power consumption and increase in the data transmission speed. The design layout of the simulation will be carried on the tanner tools 0.18um CMOS technology.

Other Details:

Manuscript Id	:	IJSTEV2I12205
Published in	:	Volume : 2, Issue : 12
Publication Date	:	01/07/2016
Page(s)	:	441-446

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