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Design and Implementation of IP Core for CAN Protocol


Manjunath Savadatti , Department of VLSI Design and Embedded Systems Centre for PG Studies, Visvesvaraya Technological University, Belagavi, Karnataka, India ; Prof. Dr. Meghana Kulkarni, Department of VLSI Design and Embedded Systems Centre for PG Studies, Visvesvaraya Technological University, Belagavi, Karnataka, India


CAN, Xilinx, CSMA/CD+AMP, FPGA, transceiver, CRC


The rapid development in designing of IP cores in the field of VLSI motivated the design engineer to integrate the complex systems of several million transistors in a single chip. The individual IP core has special features with regard to communication happening between devices or modules, accessing mechanism, functionality and reliability. CAN is a serial network technology that is widely used in real time automation control. It is a multi-master serial bus protocol that uses broadcast to transmit to CAN nodes. The design of CAN (Control Area Network) protocol it’s designing in Verilog HDL is presented. The arbitration mechanism is used to give access to the devices according to the Arbitration on Msg Priority (CSMA/CD+AMP). In this paper explained the design of CAN protocol for Physical layer and data link layer. To accomplish the entire protocol frame, the internal frame fields are designed. CAN main data frame includes, SOF, arbitration field, CF, data field, CRC field, Acknowledgement field and end of frame. Its data transfer size is limited to 8 bytes. All specifications are taken care of designing each of the frame field and also consider the time slot for each bit transfer and receive. It reduces the wiring complexity and additionally gives a flexibility to connect many devices using a single bus. Two FPGA boards are used to demonstrate the working of IP communication between the Nodes which are connected to the Bus with using two wires. Upon IP core on FPGA, each FPGA kit will act as a TRANSCEIVER. The Designing of CAN IP core using XDS 14.7 and Implementation on FPGA using Spartan 3 XC3S200 as one node and Spartan 6 XC6SLX9 as another node.

Other Details:

Manuscript Id :IJSTEV2I12120
Published in :Volume : 2, Issue : 12
Publication Date: 01/07/2016
Page(s): 194-200
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