Design of Index based Round Robin Arbiter for NOC Router

Author(s):

Kavyashree A , CENTER FOR PG STUDIES, VISVESVARAYA TECHNOLOGICAL UNIVERSITY, BELAGAVI, KARNATAKA, INDIA; Mahesh Neelagar, CENTER FOR PG STUDIES, VISVESVARAYA TECHNOLOGICAL UNIVERSITY, BELAGAVI, KARNATAKA, INDIA

Keywords:

Round robin arbiter, IRRA, Delay, Power consumption

Abstract:

Network-on-chip (NOC) is one of the scalable on-chip communication systems which are used to meet the communication demands of large number of System on chip (SoC) cores. In NOC architecture, router is a main factor which transmits data from source to destination. In router design, arbiter is important due to its performance and efficiency of NOC systems. Round robin arbiter (RoR) is a type of arbiter used in router; there are 3 different existing designs of round robin arbiter such as Parallel round robin arbiter (PRRA), Improved PRRA (IPRRA) and High speed and decentralized round robin arbiter (HDRA) and there is a high demand for low power consumption, low delay and high speed operations. Hence, in this project we proposed an Index based round robin arbiter (IRRA), which works with an index format of the input ports to reduce the power consumption, delay of the circuit. The proposed method is compared with PRRA and HDRA for delay and power consumption. Finally, the minimum number of optimizing parameters such as delay and power consumption is achieved. The design of Index based round robin arbiter is coded in Verilog, synthesized and simulated in Xilinx ISE Design Suite 12.4 tool.

Other Details:

Manuscript Id	:	IJSTEV2I12105
Published in	:	Volume : 2, Issue : 12
Publication Date	:	01/07/2016
Page(s)	:	244-249

Download Article