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High Voltage Junctionless FET with Improved DC Performance Compared to LDMOS


Author(s):

Ashish Kumar , Indian Institute of Technology Delhi; Palash Nag, Indian Institute of Technology Delhi; M. Jagadesh Kumar, Indian Institute of Technology Delhi

Keywords:

Junction less FET (JLFET), LDMOS, Power, High Voltage, ON-Resistance, Trans conductance, Breakdown Voltage, ON-state current

Abstract:

In this paper, using 2D simulations, we propose a high voltage double gate junction less field effect transistor (JLFET) with an OFF-state breakdown voltage similar to that of a conventional LDMOS. Our simulation results indicate that the proposed JLFET shows approximately twice the ON-state current compared to the LDMOS and has a high ON-state breakdown voltage (~200V). It also exhibits a lower ON-resistance and a better trans conductance. Therefore, the proposed JLFET is expected to be a low cost and better performing replacement to the LDMOS.


Other Details:

Manuscript Id :IJSTEV2I11315
Published in :Volume : 2, Issue : 11
Publication Date: 01/06/2016
Page(s): 781-784
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