VHDL Based  Serial Communication Interface Inspired By 9-Bit Uart

Fatema Anjum; Prof.Pooja Thakre

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25-Dec-23

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VHDL Based Serial Communication Interface Inspired By 9-Bit Uart

Author(s):

Fatema Anjum , Nuva College of Engineering and Technology Nagpur, India; Prof.Pooja Thakre , Nuva College of Engineering and Technology Nagpur, Maharashtra, India

Keywords:

prescalar; uart; serial communication; fifo; buffer; asynchronous

Abstract:

Serial transmission is normally used with modems and for non-networked communication between computers, terminals and other devices. Fast, secure, reliable and long distance communication is crucial to meet user requirement. Universal Asynchronous Receiver Transmitter (UART) is widely used in serial data communication because of its advantages of high reliability, long distance and low cost. In this paper, we have presented the important modules of UART for reliable, efficient and secure data transmission. We have presented baud rate generator, also known as prescaler and asynchronous first in first out (FIFO) buffer for smooth data transmission. Simulation result and register transfer view of both modules are presented in this paper.