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Design of Low Power Carry Select Adder By Using VHDL


Author(s):

Prof.N.Panchbudhe , Dr. Babasaheb Ambedkar College of Engineering and Research,Nagpur; Ankita Pashine, Dr. Babasaheb Ambedkar College of Engineering and Research,Nagpur; Bhumika Wasu, Dr. Babasaheb Ambedkar College of Engineering and Research,Nagpur; Minal Fiske, Dr. Babasaheb Ambedkar College of Engineering and Research,Nagpur; Rasika Kedar, Dr. Babasaheb Ambedkar College of Engineering and Research,Nagpur

Keywords:

CSLA, RCA, BEC, VHDL, XILINX ISE

Abstract:

In digital circuitry, fast adder is required to carry out computations in various chips like DSP processors. Carry Select Adder (CSLA) is one of the fast adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, there is scope for reducing the area and power consumption. This uses a simple and efficient gate -level modification to significantly reduce the area and power of the CSLA. Based on this modification 32-bit CSLA architecture has been designed and compared with the 32-bit conventional CSLA architecture. The modification uses Binary-To-Excess-1Converter logic instead of the chain of Ripple carry adder where the carry bit is 1.This logic has less number of gates as compared to the design without using binary to excess 1 converter logic. The modified circuit is designed and verified on Xilinx ISE design suite 14.3.The power is calculated on Xilinx Power Estimator tool. The area comparison is completed with respect to respect of LUTs .Proposed design has reduced area and power as compared with the conventional CSLA. The thesis evaluates the performance of the design in terms of area and power. The result analysis shows that the proposed CSLA structure is quantitatively superior over standard CSLA in terms of area and power.


Other Details:

Manuscript Id :IJSTEV2I10130
Published in :Volume : 2, Issue : 10
Publication Date: 01/05/2016
Page(s): 525-529
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