AN EFFICIENT HIGH SPEED VLSI ARCHITECTURE BASED 16-POINT ADAPTIVE SPLIT RADIX-2 FFT ARCHITECTURE

S.Monica Devi; Dr.T.Yasodha

CALL FOR PAPERS : Oct-2020

Submission Last Date

25-Oct-20

Submit Manuscript Online

FOR AUTHORS

FOR REVIEWERS

ARCHIEVES

DOWNLOADS

Open Access

AN EFFICIENT HIGH SPEED VLSI ARCHITECTURE BASED 16-POINT ADAPTIVE SPLIT RADIX-2 FFT ARCHITECTURE

Author(s):

S.Monica Devi , Christian College of Engineering and Technology Oddanchatram, Tamilnadu-624619, India; Dr.T.Yasodha, Christian College of Engineering and Technology Oddanchatram, Tamilnadu-624619, India

Keywords:

VLSI Architecture, Adaptive Split Radix-2, Pipelined FFT, MIMO-OFDM Communication, Parallel Multiplier

Abstract:

Now a day, the MIMO-OFDM communication industry field is mainly focused by high data transfer and more channel capacity in mobile communication. Our proposed work is to design the VLSI architecture based radix-2 based architecture. The real time pipelined FFT architecture have mainly been adopted to address the difficulties due to their attractive properties, such as small chip area, high throughput, and high speed operation. Here, the signal input can be given as a data bit which can be split into real and imaginary bit selection. Then it undergoes pre-stage transformation process which includes carry select adder/ carry look ahead subtract or architecture & weighted equation constant bits. Here the parallel multiplier is used without register, so that the time delay can be reduced compared to existing system. This system consists of Radix-2 FFT which can optimize the number of multiplier count level. This system can increase the speed and reduce the power and system complexity.