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Verilog Modeling of Wi-Fi MAC Layer for Transmitter


Author(s):

G DAVID RAJ , PBR VITS,KAVALI.; A.MAHESWARA RAO, Professor, PBRVITS, KAVALI; S.VARADARAJAN, Professor;SVU College of Engineering,Tirupati

Keywords:

Wi-Fi MAC layer, IEEE 802.11b, Header block, FPGA, Logic analyzer

Abstract:

The main objective is to design and implementation WIFI MAC Transmitter using Verilog.For the wireless communication in RF range IEEE 802.11 is one of the many standards available .IEEE 802.11b defines the Medium Access Control Layer for wire less local area networks. Wi-Fi MAC transmitter module is divided into 5 blocks I.e.. data unit interface block, controller block, payload data storage block, MAC header register block, data processing block.In this project, we are considering only two blocks i.e. payload data storage block, data processing block.


Other Details:

Manuscript Id :IJSTEV1I3001
Published in :Volume : 1, Issue : 3
Publication Date: 01/10/2014
Page(s): 1-6
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